Dr. Cliff Hou Unveiled Cloud Alliance at 2018 OIP Ecosystem Forum.
Microsoft Keynote highlighted Cloud partnership with TSMC.

TSMC Celebrates 10TH Anniversary for OIP

Introducing Semiconductor Design Service on the Cloud for the First Time
Jason S.T. Chen

TSMC celebrated the 10th anniversary of Open Innovation Platform® (OIP) in 2018. TSMC North America Chief Executive Officer David Keller unveiled the theme of “Collaborating at a New Level” during the OIP Ecosystem Forum in California, and Dr. Cliff Hou, TSMC Vice President of Technology Development made the official announcement the 5th OIP Alliance – the Cloud Alliance. The inaugural members, Amazon Web Services (AWS), Cadence, Microsoft Azure, and Synopsys, have worked with TSMC to drive a new industry partnership to pave the way for future innovations. Followed with invited keynote by Kushagra Vaid, Microsoft General Manager & Distinguished Engineer of Azure Infrastructure, highlighting the new collaboration with TSMC in Cloud computing to facilitate customer’s adoption of Cloud resources and apply them securely in their semiconductor designs.

Cloud Alliance Boosts OIP Productivity

OIP brings together the semiconductor design community, TSMC’s ecosystem partners, TSMC’s Intellectual Property (IP), design implementation, Design for Manufacturability (DFM) capabilities, process technology and backend packaging & testing services. There are currently five OIP Alliances, including the EDA Alliance, IP Alliance, DCA Alliance, VCA Alliance and the newly announced Cloud Alliance.

Dr. Cliff Hou, TSMC Vice President of Technology Development, highlighted that collaboration between TSMC and the Cloud Alliance on the development of OIP Virtual Design Environment (VDE) will provide a complete system-on-chip (SoC) design environment for semiconductor customers to design securely in the Cloud, together with TSMC OIP design infrastructures within the Cloud services. This helps customers to further enhance productivity by leveraging the power and flexibility of the Cloud and shorten the cycle time of time-to-market.

The 5TH OIP Alliance – the Cloud Alliance

Three Major Benefits of the Cloud Solution

TSMC OIP Virtual Design Environment (OIP VDE) Lowers Entry Barrier for Customer’s Adoption of Cloud Usage

TSMC has also become a Cloud service user by conducting foundation IP development on the Cloud for its most advanced technology nodes. By leveraging tens of thousands of CPU cores on the Cloud, TSMC is now able to better manage development and ensure on-time delivery during peak demand, while achieving higher quality and conducting more effective Power, Performance and Area (PPA) optimization. TSMC continues to develop OIP solutions that can assist customers to innovate and successfully roll out their products with higher quality and lower energy consumption through integration of different kinds of R&D resources and strong collaboration with ecosystem partners.

Customers Adopt TSMC’s Latest Technologies and OIP Solutions

In addition to the announcement of Cloud Alliance, Dr. Cliff Hou highlighted the status of customer’s adoption of design enablement platforms in advanced technologies and corresponding OIP solutions. TSMC continues to provide a comprehensive portfolio of EDA and IP solutions with the goal of improving customer’s first-time silicon success in the latest technologies by meeting design requirements at various stage and speeding up the realization of the innovation ideas.

Latest Technologies OIP Solutions
5nm Technology
  • EDA & IP were validated for early development in Mobile and HPC applications.
7nm Technology
  • EDA & IP have been fully validated and deployed in customer tape-outs for volume production.
7nm+ Technology
  • An enhanced version from 7nm with EDA & IP solutions deployed in leading customer tape-outs.
22nm Technology
  • The industry’s most complete 22nm technology platform that provides enhanced RF capabilities and enables competitive low power analog designs for IoT applications.
Automotive Design Enablement
  • 16FFC automotive design enablement platform has been adopted in customer’s production designs

  • 7nm automotive design enablement platform also meets functional safety and reliability requirements with EDA & design methodology and TSMC & ecosystem IPs. It has been adopted by TSMC’s customers in early automotive designs.
Wafer Level System Integration Technology
  • The readiness of TSMC’s 3DIC reference design flows support various wafer level system integration technologies, including Chip on Wafer on Substrate (CoWoS), Integrated Fan-Out on Substrate (InFO_oS), Integrated Fan-Out with Memory on Substrate (InFO_MS), Integrated Fan-Out Package on Package (InFO_PoP), Wafer On Wafer (WoW), and System On Integrated Chips (SOIC) that cover a wide range of applications.