TSMC Pioneers on Industry-academia Collaboration, Contributing to the Success of First 16nm Chip Developed through Its University Shuttle Program
TSMC continues to expand R&D activities to maintain its leadership in semiconductor technologies. As the development of TSMC's advanced process technology is moving forward at full throttle, TSMC launches the University Shuttle Program to share its process technologies with university professors and students for research, while maintaining the protection of TSMC proprietary information. The program greatly bridges the gap between academia and industry. As of September 2021, a total of 21 world’s top universities have joined this program, including National Taiwan University, National Tsing Hua University, National Yang Ming Chiao Tung University, Massachusetts Institute of Technology, Stanford University, University of California, Berkeley (UC Berkeley), and University of California, Los Angeles (UCLA). Fields of research covered topics including 5G and mobile communications, memory application, Artificial Intelligence, wearable devices, security applications, biotechnology, low-energy-consumption technologies, and many more.
In 2020, TSMC expanded the architecture of Virtual Design Environment (VDE) in the cloud and made it available to schools, which was originally intended only for customers. After eliminating the information security concerns, universities now can access the database of TSMC’s advanced technology process via VDE remotely and leverage those resources for their IC design research and teaching. This innovative cloud-based platform has helped schools to take a stride directly into 16nm FinFET technology for the first time, by two to three generations ahead of previously available process technologies to schools on 40nm and 28nm.
TSMC VDE Workflow
To amplify the impact of TSMC's University Shuttle Program, TSMC offered its 16nm FinFET technology to universities, starting from the Stanford University in the United States, a long-term collaborator of TSMC. A research team led by Dr. Mark Horowitz of Stanford's Electrical Engineering Department was the first to adopt the Virtual Design Environment (VDE) for the AI accelerator chips design and research on TSMC’s 16nm FinFET technology for deep neural network (DNN) based applications. The research team transmitted the IC design layout files through VDE to TSMC and completed tape-out. Through TSMC's University Shuttle Program, the IC design was realized in actual silicon. This is the first 16nm chip created by academia through TSMC University Shuttle Program and it advanced AI research in a big way. Meanwhile, another long-time partner, the UCLA research team has also started the RF circuits research on TSMC’s 16nm FinFET process technology via TSMC VDE, which is under the guidance of distinguished professor Dr. Mau-Chung Frank Chang.
TSMC University Shuttle Program Accelerates Next-Generation IC Designs
In 2021, TSMC further extended the application of TSMC VDE to more domestic and foreign universities, including National Taiwan University and National Yang Ming Chiao Tung University, to support their research on 5G communication circuit and baseband processor. TSMC will continue to optimize the application of VDE and support the professors and students from more top universities to access TSMC's industry-leading FinFET process technology. Through the industry-academia collaboration, TSMC looks forward to unleashing silicon innovations, enabling the next-generation IC designs from universities, and driving the semiconductor technology development.
Through VDE, the first 16nm FinFET University Shuttle Program chip tape-out was achieved. Stanford University and TSMC have created an innovative model for industry-academia collaboration that amplifies top research results by integrating advanced industrial process technology. It inspires more innovation to become a reality in the semiconductor industry.
TSMC University Shuttle Program in conjunction with the Virtual Design Environment in the cloud is simply an unprecedented combination. Students get to realize their innovative ideas using industry-leading advanced process technology. It is an incentive to attract more talents to join the semiconductor industry.