TSMC Leads the Industry by Hosting the First "TSMC IC Layout Contest" in the Cloud
In the era of advanced process technologies, the quality of chip layout affects overall performance by as much as 20%. In order to extend Moore's Law and ensure the optimization of chip performance and low power consumption, TSMC is taking the lead in the industry and actively cultivating top-notch chip layout talent with Design & Technology Co-Optimization (DTCO). In September 2019, TSMC held the first nationwide "IC Layout Contest" in Taiwan, providing extensive online training courses and corresponding EDA IC design tools and virtual environment free of charge. This contest attracted a total of 1,000 students from 35 universities across the country to compete for generous cash prizes, as well as priority status for selection to TSMC summer internship opportunities. A team from Yuan Ze University emerged from the pack and won the championship in the final contest in January 2020.
Five Firsts Achieved by TSMC IC Layout Contest
Constructing a Cloud-based Design Environment to Create a New Model of Online Learning and Competition
The first "TSMC IC Layout Contest" set a number of industry records. First, in order to create a platform for competition and learning, TSMC teamed up with the Cloud Alliance partners of the Open Innovation Platform® (OIP), Microsoft Azure, and Cadence to build a groundbreaking "Virtual Design Environment" (VDE) exclusively for the contestants. The VDE offered an unprecedented cloud-based learning space for 12-weeks, with hands-on practice courses and a competition environment for students. Secondly, the contest enabled the participating students to learn from TSMC technical experts face-to-face, and benefit from first-hand industry experiences. During the four-month competition, TSMC offered a series of training workshops, as well as online and offline courses, inspiring students' interest and widening their horizons for the latest semiconductor process technology development and chip layout technology. Through all of these measures, we cultivated the next generation of talents for the industry in the systematic way.
For the first time, TSMC launched the “TSMC IC Layout Contest” to not only provide comprehensive online training courses to large number of students, but also multiple rounds of physical workshops to guide them to fully grasp the essence of advanced process technology and enter the field of leading node layout innovations. We warmly welcome students to embrace the world-class challenges in this international arena together with TSMC.
TSMC IC Layout Contest Summary
|Pre-contest University Roadshow||
|Training Courses and Enablement||7 hours Cooperated with OIP cloud alliance partners to provide students with seven hours of the most advanced online training course on layouts skill and EDA software|
|12 weeks Provided VDE IC design practice environment in the Cloud for 12 weeks|
|3 workshops TSMC technical experts taught key layout technologies and answered questions from participating students|
|8 hours face-to-face course Advanced training workshop for the teams in the final contest. TSMC's layout experts provided guidance on advanced layout skills and reviewed the problem solving and thinking processes of the preliminary contest|
|Competition Summary||Preliminary Contest 250 teams totaling 500 students selected|
|Final Contest 17 teams, 34 students|
The teams that advanced to the final contest included first-tier universities, science and technology universities, and private universities like us. Before signing up for the contest, we were worried that we would not even have the opportunity to sign up. We were very excited to make it all the way to the end, from online training, workshops, preliminary contest, and eventually winning the first place in the final contest. We are grateful to TSMC for enabling all our persistent efforts to be seen. We strongly believe that TSMC is the company that values us purely on the basis of merit, and we are now more confident than ever going into the future!
I started circuit design and chip layout research in my undergraduate years. But I didn’t realize the need to combine process technology and chip design expertise to save area and achieve better performance for both digital and analog layout until I participated in the “TSMC IC Layout Contest " workshop. Thank you TSMC for providing such an opportunity to enrich our knowledge of IC Layout.